NOTICE: This Document was reapproved with minor editorial changes. Defects induced by thermal processing of silicon wafers may adversely influence device performance and yield. These defects are influenced directly by contamination, ambient atmosphere, temperature, time at temperature, and rate of change of temperature to which the specimens are subjected. Conditions vary significantly among device manufacturing technologies. The thermal cycling procedures of this Practice are intended to simulate basic device processing technologies. Oxidation cycles other than specified herein, or multiple oxidation cycles, may sometimes more accurately simulate device-processing procedures. The results obtained may differ significantly from those obtained with the specified oxidation cycles. The geometry of some patterns revealed by this Practice suggests that they are related to the crystal growth process while others seem related to surface preparation or thermal cycling conditions. This Practice is suitable
NOTICE: This Document was reapproved with minor editorial
changes.
Defects induced by thermal processing of silicon wafers may
adversely influence device performance and yield.
These defects are influenced directly by contamination,
ambient atmosphere, temperature, time at temperature, and rate of change of
temperature to which the specimens are subjected. Conditions vary significantly
among device manufacturing technologies. The thermal cycling procedures of this
Practice are intended to simulate basic device processing technologies.
Oxidation cycles other than specified herein, or multiple oxidation cycles, may
sometimes more accurately simulate device-processing procedures. The results
obtained may differ significantly from those obtained with the specified
oxidation cycles.
The geometry of some patterns revealed by this Practice
suggests that they are related to the crystal growth process while others seem
related to surface preparation or thermal cycling conditions.
This Practice is suitable for acceptance testing when used
with referenced practices and methods.
This Practice covers the detection of crystalline defects
in the surface region of silicon wafers. The defects are induced or enhanced by
oxidation cycles encountered in normal device processing. An atmospheric
pressure oxidation cycle representative of bipolar, metal-oxide-silicon (MOS)
and CMOS technologies is included. This Practice reveals strain fields arising
from the presence of precipitates, oxidation induced stacking faults, and
shallow etch pits. Slip is also revealed that arises when internal or edge
stresses are applied to the wafer.
Application of this Practice is limited to specimens that
have been chemical or chemical/mechanical polished to remove surface damage
from at least one side of the specimen. This Practice may also be applied to
detection of defects in epitaxial layers.
The surface of the specimen opposite the surface to be
investigated may be damaged deliberately or otherwise treated for gettering
purposes or chemically etched to remove damage.
Referenced SEMI Standards (purchase separately)
SEMI C28 — Specification for Hydrofluoric Acid
SEMI C54 — Specification and Guide for Oxygen
SEMI C58 — Specification for Hydrogen
SEMI M59 — Terminology of Silicon Technology
SEMI MF1809 — Guide for Selection and Use of Etching
Solutions to Delineate Structural Defects in Silicon
SEMI MF1810 — Test Method for Counting Preferentially
Etched or Decorated Surface Defects in Silicon Wafers
Revision History
SEMI MF1727-1110 (Reapproved 0322)
SEMI MF1727-1110 (Reapproved 1115)
SEMI MF1727-1110 (technical revision)
SEMI MF1727-0304 (technical revision)
SEMI MF1727-02 (first SEMI publication)
NOTICE: This Document was reapproved with minor editorial
changes.
Defects induced by thermal processing of silicon wafers may
adversely influence device performance and yield.
These defects are influenced directly by contamination,
ambient atmosphere, temperature, time at temperature, and rate of change of
temperature to which the specimens are subjected. Conditions vary significantly
among device manufacturing technologies. The thermal cycling procedures of this
Practice are intended to simulate basic device processing technologies.
Oxidation cycles other than specified herein, or multiple oxidation cycles, may
sometimes more accurately simulate device-processing procedures. The results
obtained may differ significantly from those obtained with the specified
oxidation cycles.
The geometry of some patterns revealed by this Practice
suggests that they are related to the crystal growth process while others seem
related to surface preparation or thermal cycling conditions.
This Practice is suitable for acceptance testing when used
with referenced practices and methods.
This Practice covers the detection of crystalline defects
in the surface region of silicon wafers. The defects are induced or enhanced by
oxidation cycles encountered in normal device processing. An atmospheric
pressure oxidation cycle representative of bipolar, metal-oxide-silicon (MOS)
and CMOS technologies is included. This Practice reveals strain fields arising
from the presence of precipitates, oxidation induced stacking faults, and
shallow etch pits. Slip is also revealed that arises when internal or edge
stresses are applied to the wafer.
Application of this Practice is limited to specimens that
have been chemical or chemical/mechanical polished to remove surface damage
from at least one side of the specimen. This Practice may also be applied to
detection of defects in epitaxial layers.
The surface of the specimen opposite the surface to be
investigated may be damaged deliberately or otherwise treated for gettering
purposes or chemically etched to remove damage.
Referenced SEMI Standards (purchase separately)
SEMI C28 — Specification for Hydrofluoric Acid
SEMI C54 — Specification and Guide for Oxygen
SEMI C58 — Specification for Hydrogen
SEMI M59 — Terminology of Silicon Technology
SEMI MF1809 — Guide for Selection and Use of Etching
Solutions to Delineate Structural Defects in Silicon
SEMI MF1810 — Test Method for Counting Preferentially
Etched or Decorated Surface Defects in Silicon Wafers
Revision History
SEMI MF1727-1110 (Reapproved 0322)
SEMI MF1727-1110 (Reapproved 1115)
SEMI MF1727-1110 (technical revision)
SEMI MF1727-0304 (technical revision)
SEMI MF1727-02 (first SEMI publication)
QC-652S Melt Flow Index ( ASTM D1238, ASTM D3364, ISO 1133 )
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